Explainer
What Is RISC-V? The Open Instruction Set Explained
RISC-V is an open standard for the instructions a processor understands. It is pronounced risk-five. Anyone can build a chip that follows it without paying a fee for the instruction set. That has made it popular for small controllers and, more recently, a serious option for larger processors. This guide explains what it is and what it does and does not change.
What an instruction set is
An instruction set architecture, or ISA, is the list of basic commands a processor understands, such as add, load a value from memory, or jump to another place in the program. It is the contract between software and hardware. A program built for one ISA will not run directly on a chip that uses another.
Two ISAs dominate today. x86 is used in most PCs and servers and comes from Intel and AMD. Arm is used in most phones and increasingly in servers and laptops. Both are proprietary. Arm licenses its designs and architecture to other companies for a fee.
RISC stands for reduced instruction set computer, a design style that uses a small set of simple instructions. The V is the Roman numeral five, because this was the fifth RISC design from the University of California, Berkeley.
What makes RISC-V open
RISC-V began at Berkeley around 2010 as a teaching and research project. The specification is now maintained by RISC-V International, a non-profit organisation. Its members include chip makers, software firms and universities.
Open here means the ISA specification is public and free to implement. It does not mean every RISC-V chip is open or free. A company can design a RISC-V core and keep the design secret and sell it. Several companies do exactly that.
The ISA is modular. There is a small base integer set, such as RV32I for 32-bit designs and RV64I for 64-bit designs. Optional extensions add features such as multiplication, floating-point maths, compressed instructions and vector operations. Designers can also add custom instructions for their own needs, which is much harder, or not allowed, with the other major ISAs.
To keep software compatible, the community defines profiles, which are agreed bundles of extensions. A profile such as RVA23 gives operating system and software developers a stable target for application processors.
Who builds on it
SiFive was founded by some of the Berkeley researchers behind the ISA and licenses RISC-V cores. Andes Technology and StarFive are other well-known suppliers of cores and chips.
Espressif uses RISC-V in some of its low-cost wireless microcontrollers. Tenstorrent, led by chip designer Jim Keller, builds RISC-V based AI hardware. Semidynamics licenses RISC-V cores with vector units. Ventana Micro Systems designed RISC-V server chiplets and has been acquired by Qualcomm. Many storage controllers, sensors and accelerator control blocks quietly use RISC-V cores too.
Governments and regional groups also back RISC-V. China and Europe in particular see it as a route to chip design that does not depend on a single foreign licensor.
Why it matters for CPUs
The first benefit is cost and freedom. A company that designs its own core does not pay an ISA licence fee and does not need permission to change its design.
The second is customisation. A chip for a specific job, such as AI inference or a motor controller, can add instructions tuned to that job.
The third is supply-chain independence. A standard owned by a non-profit is harder for any single company or country to withdraw.
The fourth is simply competition. A free ISA lowers the cost of starting a processor company, which should bring more designs to market.
The limits
An open ISA is only a starting point. A competitive CPU needs a good microarchitecture, which is how the core is actually built inside, along with strong manufacturing, firmware and software. The ISA is a small part of that cost.
Software is the main barrier. Decades of operating systems, compilers, libraries and applications have been tuned for x86 and Arm. RISC-V support in Linux and the main compilers is good and growing, but the ecosystem is younger, and many commercial applications are not yet available for it.
Fragmentation is a risk. Because the ISA allows custom extensions, two RISC-V chips may not run the same software. Profiles exist to limit this problem.
Performance is also still catching up. In 2026 the fastest RISC-V cores generally trail the best Arm and x86 cores, though the gap is narrowing.
What to expect
RISC-V is already established in embedded devices and is spreading into AI accelerators, where it often runs the control logic around the main compute engines. Servers, phones and laptops are the harder frontier because they depend on a large software base.
When assessing a RISC-V company, look at the core's measured performance, the profile it supports, the state of operating system support, and the customers shipping in volume.
Companies mentioned
- SiFive SiFive designs processor cores based on RISC-V, an open instruction set that any company can use without paying a fee for the architecture itself. It mainly licenses these designs to chip makers, who build them into their own products. In January 2026 it said it would integrate Nvidia's NVLink Fusion, an interconnect that links processors to Nvidia GPUs, into its data centre platforms. SiFive was founded in California in 2015 and is fabless, meaning it does not run its own factories.
- Andes Technology Andes Technology licenses processor intellectual property based on the RISC-V instruction set, selling its AndesCore designs to chip makers who build them into their own SoCs. The portfolio ranges from small 32-bit embedded cores to 64-bit out-of-order multicore designs, with vector and automotive safety variants. It is a founding premier member of RISC-V International. The company is headquartered in Hsinchu, Taiwan, and has been listed on the Taiwan Stock Exchange under code 6533 since 2017.
- Tenstorrent Tenstorrent designs AI processors and licenses RISC-V and AI intellectual property to customers building their own silicon. Its Wormhole and Blackhole accelerator cards are built around Tensix compute cores, and Blackhole adds on-die RISC-V cores for orchestration without a separate host processor. The company also sells developer systems such as the TT-QuietBox and larger Galaxy servers. Tenstorrent is led by chip architect Jim Keller and emphasizes open-source software and the royalty-free RISC-V instruction set.
- Ventana Micro Systems Ventana Micro Systems designed high-performance RISC-V processor cores and chiplets for data centres under the Veyron name. RISC-V is an open instruction set that any company can use without licensing fees, unlike Arm designs. Chiplets are small dies combined in one package. Ventana was founded in 2018 and was based in Cupertino, California. Qualcomm announced in December 2025 that it had acquired the company, with financial terms undisclosed, to add to its own CPU and RISC-V engineering.
- Codasip Codasip develops RISC-V processor IP, meaning licensable processor designs that chipmakers build into their own products. It also offers Codasip Studio, a toolset for customising processors using its CodAL description language, and CHERI memory protection technology aimed at silicon security. Its markets include automotive, industrial, defense and IoT. The company was founded in 2014 by Karel Masarik and is privately held. In July 2025 its board started an expedited process to sell the company.
- Semidynamics Barcelona company founded in 2016 by Roger Espasa that licenses 64-bit RISC-V cores with vector units: the in-order Avispado and the out-of-order Atrevido (Atrevido 423 released July 2023; Atrevido A426 now listed). Its website now also offers the Cervell NPU and a terabyte-scale AI inference unit (AIPU).
- StarFive StarFive, formally Shanghai StarFive Semiconductor Technology, designs RISC-V processors. It licenses CPU and network-on-chip IP, which are ready-made design blocks, and sells its own chips, including the JH7110 application processor, a baseboard management controller chip and microcontrollers. It also sells VisionFive single-board computers and development kits, and publishes an open-source Linux SDK. The company is based in Shanghai. Production status of newer chips and its founding year were not confirmed.
- Akeana Akeana is a RISC-V processor IP company. RISC-V is an open instruction set, and Akeana licenses processor core designs that other firms build into their own chips. It came out of stealth in August 2024 with three core families, from 32-bit designs to high-performance 64-bit cores, along with supporting blocks such as a cache and an AI matrix engine. The company was founded in 2021 by a team with server chip design experience and is based in San Jose, California.
- Syntacore RISC-V processor IP company established in 2015. Its cores range from the open-source 32-bit SCR1 microcontroller core to the SCR7 and SCR9 Linux-capable application cores, and it sells tools, an FPGA SDK and design services. Yadro took control of the company in 2019. A November 2025 article describes its SCR1, SCR3, SCR4 and SCR6 MCU-class cores.
- Arm Holdings Arm designs processor cores and related designs for GPUs and neural processing units, and licenses them to other companies instead of selling most chips itself. Licensees such as phone and server chip makers build the designs into their own silicon. This licensing model separates it from firms like Intel or AMD that make and sell finished processors. Arm is headquartered in Cambridge, England, was founded in 1990 as a joint venture of Acorn Computers, Apple and VLSI Technology, and has been majority owned by SoftBank Group since 2016. It listed on Nasdaq in September 2023.
Company details come from the Compute Compass directory and may be out of date. This is not investment advice.