About Verific Design Automation
Verific Design Automation sells parser software, the front-end components that read chip design files so other tools can analyze them. Its platforms handle SystemVerilog, VHDL and UPF, which are standard languages for describing circuits and their power intent. They are delivered as C++ source code that makers of design tools build into their own products. Unlike full design suites, Verific supplies only this reading layer. Its site lists users from small design-tool startups to large semiconductor firms, including AMD, Arm, Cadence, Nvidia, Siemens and Synopsys.
Verific Design Automation was founded in 1999 and is based in San Jose, CA, United States. It is listed under ASICs, FPGAs.
Compute Technologies
- ASICs
- FPGAs
What Verific Design Automation works on
ASICs
An ASIC, or application-specific integrated circuit, is a chip designed to do one job or a narrow set of jobs. Its circuits are fixed when the chip is made. A CPU can run any program; an ASIC does what it was designed for and nothing else.
FPGAs
An FPGA, or field-programmable gate array, is a chip whose internal wiring can be changed after it is made. It contains a grid of small logic blocks, memory blocks and programmable connections. Loading a new configuration file, called a bitstream, turns it into a different digital circuit.
